TY - JOUR
AU - Mertens, Jan Cedric
AU - Boschmann, Alexander
AU - Schmidt, M.
AU - Plessl, Christian
ID - 6516
IS - 4
JF - Sports Engineering
SN - 1369-7072
TI - Sprint diagnostic with GPS and inertial sensor fusion
VL - 21
ER -
TY - GEN
AB - Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.
In this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.
This FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.
AU - Ramaswami, Arjun
ID - 5417
KW - FFT: FPGA
KW - CP2K
KW - OpenCL
TI - Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA
ER -
TY - JOUR
AB - Approximate computing has shown to provide new ways to improve performance
and power consumption of error-resilient applications. While many of these
applications can be found in image processing, data classification or machine
learning, we demonstrate its suitability to a problem from scientific
computing. Utilizing the self-correcting behavior of iterative algorithms, we
show that approximate computing can be applied to the calculation of inverse
matrix p-th roots which are required in many applications in scientific
computing. Results show great opportunities to reduce the computational effort
and bandwidth required for the execution of the discussed algorithm, especially
when targeting special accelerator hardware.
AU - Lass, Michael
AU - Kühne, Thomas
AU - Plessl, Christian
ID - 20
IS - 2
JF - Embedded Systems Letters
SN - 1943-0663
TI - Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots
VL - 10
ER -
TY - GEN
AU - Filmwala, Tasneem
ID - 5414
TI - Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform
ER -
TY - GEN
AU - Gadewar, Onkar
ID - 5421
TI - Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL
ER -
TY - CONF
AU - Riebler, Heinrich
AU - Vaz, Gavin Francis
AU - Kenter, Tobias
AU - Plessl, Christian
ID - 1204
KW - htrop
SN - 9781450349826
T2 - Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
TI - Automated Code Acceleration Targeting Heterogeneous OpenCL Devices
ER -
TY - CONF
AB - The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.
AU - Kenter, Tobias
AU - Mahale, Gopinath
AU - Alhaddad, Samer
AU - Grynko, Yevgen
AU - Schmitt, Christian
AU - Afzal, Ayesha
AU - Hannig, Frank
AU - Förstner, Jens
AU - Plessl, Christian
ID - 1588
KW - tet_topic_hpc
T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
TI - OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
ER -
TY - CONF
AB - We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.
We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.
AU - Lass, Michael
AU - Mohr, Stephan
AU - Wiebeler, Hendrik
AU - Kühne, Thomas
AU - Plessl, Christian
ID - 1590
KW - approximate computing
KW - linear algebra
KW - matrix inversion
KW - matrix p-th roots
KW - numeric algorithm
KW - parallel computing
SN - 978-1-4503-5891-0/18/07
T2 - Proc. Platform for Advanced Scientific Computing (PASC) Conference
TI - A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices
ER -
TY - JOUR
AU - Schumacher, Jörn
AU - Plessl, Christian
AU - Vandelli, Wainer
ID - 1589
JF - Journal of Physics: Conference Series
TI - High-Throughput and Low-Latency Network Communication with NetIO
VL - 898
ER -
TY - CONF
AB - Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.
AU - Kenter, Tobias
AU - Förstner, Jens
AU - Plessl, Christian
ID - 1592
KW - tet_topic_hpc
T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
TI - Flexible FPGA design for FDTD using OpenCL
ER -